Key facts
- Aisin said the chip consumes about 98% less power than similar existing chips.
- The 16nm chip embeds 32MB of STT-MRAM, removing the need for external DRAM or solid-state storage.
- The partners reported kernel startup of 65.7 milliseconds against 2,535.3 milliseconds for the conventional system.
- AI processing time fell to 58.5 milliseconds from 594.6 milliseconds in the partners' comparison.
- Detection accuracy on Tiny YOLOv3 declined to 0.316 mean average precision from 0.325.
- Part of the work came from commissioned research for Japan's NEDO public agency, according to the release.
Aisin said on Monday that it had developed a semiconductor using magnetic technology that consumes about 98% less power than similar existing chips, a result the Japanese automotive parts supplier said would help process large amounts of data more efficiently. The work was done with Tohoku University, the company said.
The chip is a 16-nanometer AI system-on-chip with 32 megabytes of embedded spin-transfer torque magnetoresistive random-access memory, or STT-MRAM, according to a release from the partners dated November 2, 2026. Embedding that memory on the chip removes the need to move operating-system boot data and AI model weights from external storage at startup, the partners said.
In the reported comparison, the conventional system needed 2,535.3 milliseconds to reach kernel startup against 65.7 milliseconds for the new design, an improvement of about 39 times. AI processing time fell from 594.6 milliseconds to 58.5 milliseconds, and the conventional approach transferred 12 megabytes of model weights from a solid-state drive to DRAM before processing.
The accelerator runs Tiny YOLOv3, a compact model that identifies objects and their positions in images. A hybrid 8-bit and 16-bit multiplication architecture and weight-sharing techniques cut model-weight storage from 17.7 megabytes to 9.36 megabytes, while mean average precision, a measure of detection accuracy, declined from 0.325 to 0.316.
The design uses near-memory computing, which places memory close to processing units to reduce data movement. The partners said memory access and transfers are constraints on speed and energy efficiency as larger AI models move into edge devices such as vehicles, robots, cameras and connected equipment.
The project brought together a team led by Professor Tetsuo Endoh at Tohoku University's Center for Innovative Integrated Electronic Systems and a team from Aisin. The chip combines a dual-core Arm Cortex-A53 CPU, an Arm Mali-G31 graphics processor, an AI accelerator and embedded STT-MRAM.
The research was scheduled for presentation at the IEEE Asian Solid-State Circuits Conference in Hsinchu, Taiwan, running from November 1 to November 4, 2026, according to the release. Part of the work resulted from commissioned research for Japan's New Energy and Industrial Technology Development Organization, the public agency known as NEDO.