Key facts
- Researchers developed a method to stack high-performance silicon circuits directly on top of one another.
- The process uses ultrathin single-crystalline silicon nanomembranes bonded at temperatures no higher than 200 degrees Celsius.
- This approach stays within the thermal budget for monolithic 3D integration, unlike previous methods.
- The technique achieved yields between 98% and 100% for stacked silicon layers containing 625 transistors each.
- The researchers demonstrated three-dimensional logic circuits and static random-access memory cells.
- The technology is being transferred to industrial semiconductor foundries with support from IBM, Intel, and TSMC.
As Moore's Law slows, the semiconductor industry faces challenges in continuing to increase computing power through traditional transistor miniaturization. Building chips vertically, known as 3D integration, offers a path to higher transistor density and improved efficiency. However, thermal constraints during manufacturing have been a significant hurdle for monolithic 3D approaches, which build layers directly on top of each other.