Key facts
- Tokyo Artisan Intelligence (TAI) is partnering with Malaysian IC design firm Oppstar to develop and mass-produce reconfigurable AI chips.
- The chips are intended for edge AI systems, targeting niche markets like railways, factories, and robotics.
- This collaboration marks a move into higher-value semiconductor activities for Malaysia.
- TAI provides AI hardware technology and final product design, while Oppstar handles chip-wide design and implementation.
- Mass production shipments are anticipated from 2028 onwards.
Japanese AI chip startup Tokyo Artisan Intelligence (TAI) is gearing up for mass production of its reconfigurable AI chips with support from Malaysian IC design firm Oppstar. The collaboration aims to develop chips tailored for AI-driven applications in niche markets such as railways, factories, and robotics, positioning TAI as a player outside the dominant data center AI race.
TAI's CEO, Hiroki Nakahara, stated that the company is preparing for mass production next year. The partnership with Oppstar, which includes Silicon X for IP cores and software development, involves a full turnkey development process. This includes chip design, package design, post-silicon validation, and outsourced semiconductor assembly and test enablement.
Oppstar's co-CEO, Ng Meng Thai, highlighted that this collaboration signifies Malaysia's advancement into higher-value semiconductor activities beyond traditional assembly and testing. He noted that such complex chip development has typically been dominated by multinational corporations, making this an important step for a local fabless chip design firm like Oppstar.
A Statement of Work (SoW) has been signed by TAI, Oppstar, and Silicon X to transition into a full-scale design and implementation phase with mass production in mind. The goal is to accelerate the realization of next-generation edge AI platforms, with mass production shipments targeted for 2028 and beyond. The reconfigurable AI semiconductor chip is based on FPGA technology, allowing its internal circuit configuration to be freely changed according to AI applications, addressing challenges in reducing power consumption and enabling flexible rewriting for edge AI devices.